The technology described in this patent document relates generally to SRAM devices and more particularly to bit line pre-charge circuitry and methods of pre-charging a bit line in an SRAM device.
Static random access memory (SRAM) is commonly used in electronic devices. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a data bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit line (or a pair of bit lines), which is used for storing a data bit into a selected SRAM cell or reading a stored data bit from the selected SRAM cell.